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YieldMaxx™

What is YieldMaxx?

• Advanced design-for-manufacturing (DFM) tool for fabless semiconductor firms.
• Patented, die-level structures provide precision, on-die measurements of key performance parameters, including threshold voltage (V_T), resistance, capacitance and on-current variations.
• Bundled PDKChek® test structure and software solution for displaying device mismatch.
• Independent solution provides framework for foundry-to-foundry comparisons.
• Prevents costly probe damage from conventional measurement methods.

Test Structure Portion

• Die-level, in-situ test structure that occupies minimal silicon area.
• Patent-protected, stand-alone, proprietary IP block that measures die-level process-induced variations.
• Measures MOS transistor threshold voltage (V_T), resistance, capacitance, and turn on/off current.
• Die-level testing takes advantage of test structures and bonding pads that are already present on the die, so there is no additional error introduced by the contact resistance of a probe station.
• Layout on the die along with the host circuit.
• Designed to extract electrical measurements from several test devices (transistors, resistors, capacitors).

GDS II layout of PDKChek®

Graphical Utility

The YieldMaxx software provides visual indications of device mismatch parameters, as shown below: