YieldMaxx™ (PDKChek®)

What is YieldMaxx?

• Patent-protected, stand-alone, proprietary IP block that measures die-level process-induced variations.
• Measures MOS transistor threshold voltage (VT), resistance, capacitance, and turn on/off current.
• Die-level testing takes advantage of test structures and bonding pads that are already present on the die, so there is no additional error introduced by the contact resistance of a probe station.
• Layout on the die along with the host circuit.
• Designed to extract electrical measurements from several test devices (transistors, resistors, capacitors).

What Can YieldMaxx Do?

• Provide circuit designers with independent verification data to improve the accuracy of process design margins, increased process yield, expedite problem resolution (design- or process-related), reduce design iterations (duration and frequency), and enable shorter time to market.
• Provides statistical distributions of the parameters including any spatial and angular variation that may exist throughout the wafer.
• Can be configured for placement on individual die or in scribeline.
• Can be ported from 90 nm down to 28 nm processes.
• Operate as foundry qualification and matching utility.

YieldMaxx Layout

YieldMaxx allows for faster testing than traditional scribeline transistors. Testing can take place before or after packaging the die. Die level testing takes advantage of test structures and bonding pads that are already present on the die, so there is no additional error introduced by the contact resistance of a probe station.