SJ BIST Features:
- Detects incipient fatigue damage to dedicated pins of FPGA packages, especially BGA packages
- Improves fault coverage without significantly increasing system complexity
- Improves fault coverage for advanced redundancy management without using redundancy techniques
- Provides positive correlation of hardware faults to intermittencies
SJ BIST is highly sensitive and can detect faults of 100 ohms or lower within a period of two clock cycles, which for a 50 MHz clock is equal to 40 nanoseconds.
The capability of SJ BIST to perform early detection and identification of an assembly likely to experience a malfunction is invaluable because: (1) damage is detected prior to catastrophic failure of the FPGA, thereby enabling mission success; and (2) corrective actions using condition-based maintenance procedures can be performed, thereby avoiding operational failures.
Additional Applications
SJ BIST provides a solution for any application and package type that uses digital read/write I/O ports. In addition to the FPGA application, SJ BIST can be used in microcontroller units (MCUs), microprocessor units (MPUs), and application-specific integrated circuits (ASICs). Applicable packages are grid arrays such as plastic type of ball grid arrays (PBGAs, PGAs, BGAs), columnar grid arrays (CGAs), and ceramic columnar grid arrays (CCGAs). SJ BIST also monitors the solder bumps located at the die attach area of a package where flip chip technology die attach technology is used.
System Architecture
Figure 1 shows the system architecture of SJBIST.
Figure 1: System Architecture
Description
The purpose of the SJ BIST (Solder Joint Built-In Self-Test™) IP core is to prognostic-enable field programmable gate arrays (FPGAs) for the detection of electronic faults resulting from degradation of the solder connections that attach the FPGA to an electronic assembly.
Prior to development of SJ BIST, there were no known methods for real-time detection of high-resistance solder joint faults associated with the input/output (I/O) port connections of FPGAs. SJ BIST is designed to detect occurrences of high-resistance events related to FPGA pin connections and to provide information to the system regarding the condition of the solder joints. When the SJ BIST prognostic is programmed into an FPGA, SJ BIST enables early detection and identification of faults leading to a malfunction. While a particular damaged I/O port connection might not result in immediate FPGA operational failure, the damage indicates the FPGA is no longer reliable.
The occurrence of a single fault is a prognostic warning to avoid a near-term operational intermittent or long-lasting fault. The early detection made possible by SJ BIST allows corrective actions to be performed with condition-based maintenance procedures, averting operational failures. In addition to prognostics, SJ BIST can be used in newly designed manufacturing reliability tests to investigate failure modes related to an assembly.
In over two years of independent testing, SJ BIST has never issued a false alarm.
The core provides:
- Examples of a 2-port, 4-port, and 8-port instantiations of SJ BIST.
- A data-register implementation to collect fault information.
Ridgetop Group, Inc. also provides consultation, design, and implementation services for integrating SJ BIST into an application.
Device Utilization and Performance
Number of Logic Elements in a 4-core, 8-pin SJ BIST Implementation: 220 to 400.
Estimated Power to Monitor 8 Pins
The estimated power to monitor pins is dependent on the driving current of the I/O ports of a specific FPGA. For a 100-MHz, 1156-pin, 1-mm pitch exemplary FPGA, the estimated power to monitor 8 pins is 150 mW.
Deliverables
- Core and examples written in Verilog and distributed as source code.
- Guide to Implementation and Use
- Expert technical support
Contact Information
For additional information, contact Ridgetop Group, Inc. at:
Ridgetop Group, Inc.
3580 West Ina Road
Tucson, AZ 85741
Tel: (520) 742-3300
Fax: (520) 544-3180
E-mail: IP@ridgetopgroup.com
URL: www.ridgetopgroup.com/partners/altera.php/
