TSV BIST™ Die-Level Integrity Monitors

TSV

Through-silicon via

2.5D ICs and 3D ICs are advanced packaging methodologies based on stacks of ICs that incorporate through-silicon vias (TSVs) for chip-to-chip communication: 2.5D ICs use an interposer to route the signals among the stacked chips, and 3D ICs use the TSVs to directly connect between the chips without the aid of an interposer. While the potential benefits of increased circuit density and performance are alluring, one of the hurdles the electronics industry must face is how to ensure the reliability of such components. These dense packages are created with new manufacturing technologies and must deal with a great deal of heat in a very small space and, without a long track record of field data to rely upon, it is difficult to project how well they will endure years into the future. This issue is magnified because some of the applications that could most benefit from 2.5D/3D IC technology – e.g., satellites, telecommunications, and transportation systems – are also among the most demanding when it comes to safety and reliability.

Ridgetop Group has developed a technology suite called TSV BIST™ which is the first to address this thorny problem. TSV BIST (BIST is an acronym for built-in self-test) consists of tiny monitors that are embedded into the 2.5D IC and 3D IC chip stacks that can detect degradation in the chip-to-chip interconnections, identify intermittencies, and ultimately warn of impending interconnect failure – before the failure actually occurs. TSV BIST incorporates and builds upon proven Ridgetop technology for board-to-package interconnection monitoring (SJ BIST™) and power and ground signal monitoring (Q-Star Test PG Mon™). TSV BIST is part of the Sentinel Interconnect™ family of products.

The following figures show how TSV BIST can be deployed as active monitors embedded in a 2.5D IC interposer (Figure 1), embedded in chips in a 2.5D IC stack (Figure 2), and embedded in chips in a 3D IC stack (Figure 3).

TSV BIST in 2.5D IC package

Figure 1. TSV BIST in 2.5D IC package – click to enlarge

TSV BIST Stacked 2.5D IC package

Figure 2. TSV BIST Stacked 2.5D IC package – click to enlarge

TSV BIST 3D IC package

Figure 3. TSV BIST 3D IC package – click to enlarge

For more information, contact us directly, or follow the links below.

White Papers

Links to conference presentations on this subject can be found in our Resource Library

Related Products

Webinars

  • Reliability Challenges in Through-Silicon Via (TSV)-based Packaging

Click here to download Dr. Chakrabarty’s webinar presentation (PDF)
Click here to download  Dr. Manhaeve’s webinar presentation (PDF)
Click here to download the audio/video recording of the webinar (WMV)

  • Reliability Challenges in Through-Silicon Via (TSV)-based Packaging

    Click here to download the Tezzaron webinar presentation (PDF)
    Click here to download the Ridgetop webinar presentation (PDF)