Ridgetop Training and Support

IC design at RidgetopRidgetop Group offers a range of training courses covering the theory and application of the various products and technologies we provide. Training is available on-site, at Ridgetop’s facilities, and over the web (when appropriate). Training may be customized to the specific organizational needs and application.

Ridgetop Group is excited to announce its new training course offerings that will be available in 2016 and 2017. These new 1 and 2-day courses are taught by the best and brightest distinguished engineers and leading mathematicians whom are well recognized throughout private, commercial, and governmental sectors:

  • T100 — Precision Semiconductor Characterization Measurements   (2 days)

Abstract: Students will learn practical methods to compare the performance of different semiconductor processes for specific, targeted application areas. Included are extracting short-channel aging phenomena such as Time Dependent Dielectric Breakdown (TDDB), Hot Carrier Injection (HCI), Stress Migration, xBTI (NBTI and PBTI) and others. Emphasis will be on supporting fabless and foundry Wafer Level Reliability (WLR) applications.

  • T200 — IVHM and Prognostics for Reliability Engineers   (2 days)

Abstract: Students will learn how to incorporate System and Subsystem degradation monitoring with conventional reliability tools to achieve higher levels of overall system reliability and performance. Issues such as sensing, anomaly detection, and determination of State-of-Health (SoH) and Remaining Useful Life (RUL) of complex aerospace, automotive and industrial systems will be covered.

  • T250 — IoT-based Sensing Strategies for IVHM Applications   (1 day)

Abstract: Students will learn practical methods of wireless sensing using internet-based protocols to remotely sense physical degradation, while eliminating the need for bulky cabling. Example protocol used will be IEEE802.15.4. Issues include IP address assignments, range of transmission, interference, robustness, time/date stamps and GPS locators.

  • T300 — Board and Module-Level No Fault Found (NFF) Methods

Abstract: Students will learn practical methods of reducing occurrences of No Fault Found (NFFs) on legacy Circuit Card Assemblies. Related terms include Could not Duplicate (SND), Bounce Rate, No Trouble Found (NTF) will also be covered. Methodology of detecting ‘soft faults’ and intermittencies to improve test coverage and increase testing throughput.

Please contact us to arrange for an on-site training course or for more information about our training course content, schedules, and availability.

Ridgetop Group’s other available training courses cover:

  • Prognostics & Health Management (PHM) Theory and Implementation

Abstract: This course provides the basic foundation in prognostics, how to extract degradation signatures, and process data to provide information that supports a comprehensive health management system.  Relevant examples of an electromechanical actuator, jet engine and module-level power systems will be used in the course.

RotoSense™ Advanced Rotary Systems Diagnostics and IoT Application

Abstract: This training class covers the theory of operation of the RotoSense wireless sensor, how to configure an effective monitoring system of rotational vibration and speed for rotary systems such as spinning shafts, epicyclic gears and wheel/axel assemblies.

SJ BIST™ Theory and Operation

Abstract: The participant will learn the theory behind the SJ BIST interconnection reliability monitor, details of its operation, and the practicalities of implementing in a board-level design or in other environments. This hands-on course also provides instruction in the HDL code for implementing SJ BIST.

Note: This course is required for all first time SJ BIST customers.

  • Semiconductor Reliability Testing with ProChek™

Abstract: The participant will learn the theory of the ProChek platform for semiconductor fabrication process characterization, details of the operation and application of the various stress / measurement units (SMUs) that are available inside the system. The student will also learn how to set up and run tests for bias temperature instability (BTI), time-dependent dielectric breakdown (TDDB), hot carrier injection (HCI), electromigration, and stress migration. Instruction will be provided on how to collect, analyze, and understand the results from these tests.

Note: This course is required for all first time ProChek customers.

  • ProChek™ Test Coupon Design and Implementation

Abstract: The participant will learn the theory of ProChek test coupon test structures, chip- and system-level control and observation switching matrix mechanisms, embedded chip-level heating structures, and general guidelines for the design, layout, and verification of these parts of the test coupon. It also covers the relative benefits and implementation strategies of the integrated (single-chip) test coupon vs. test supervisor IC (TSIC) and DUT IC approach.

Note: This course is required for all first time ProChek Test Coupon customers.

  • Design for Testability (DFT)

Abstract: The participant will have understand the relationship between design and test, know the capabilities and limitations of test, and understand the DFT measures that can be taken to improve the test process and reduce product costs. With this knowledge the participant will be able to bridge the gap between design and test and have a better understanding of the factors involved in controlling product development and implementation costs.

  • Q-Star Test™ Current Monitor Theory and Integration
  • Cost Reduction Through IDDQ

Abstract: This course provides an introduction to IDDQ test, DFT rules for IDDQ and what’s the impact of a bad DFT on IDDQ test application, IDDQ test limit setting and engineering practice, the impact of deep submicron and nanotechnologies on IDDQ testing, test pattern optimization, and covers case study discussion and results.

  • Boundary Scan Demystified

Abstract:  The participant will have an in-depth understanding of what boundary scan means, what it’s targets are, what it requires, and what benefits are offered by implementing and using a boundary scan-based Design for Test (DFT) strategy both at circuit and at system level. While not a hand-on boundary scan class, upon completion the student will have a better understanding on how to work with boundary scan tools and what benefits they offer.

  • The Quest for 0ppm

Abstract: The course provides an understanding of the capabilities and limitations of test as well as of the DFT measures that can be taken to improve the test process and reduce product costs. With this knowledge the participant will be able to bridge the gap between Design and Test and have a better understanding of the factors involved in reaching a 0ppm quality level.

 

Please contact us to arrange for an on-site training course or for more information about our training course content, schedules, and availability.

To contact Ridgetop for customer support, click here to email us or call +1 520-742-3300.