ProChek™ for Wafer-Level Reliability (WLR)

The Semiconductor Process Characterization Solution
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Ridgetop Group's ProChek is an innovative system to qualify the performance and characterize the intrinsic reliability of deep submicron nanotechnology CMOS processes for microelectronics applications. ProChek is designed to provide fast and reliable measurement of critical electrical performance parameters. Subtle variations in these parameters can have significant adverse impact on the yield and performance of chips manufactured with modern semiconductor processes. ProChek dramatically reduces the cost of gathering wafer-level data concerning common degradation effects. These effects limit the lifetime of chips manufactured with all process nodes and some are exacerbated as feature sizes shrink. It can also perform faster than traditional wafer-level test methods through support for highly parallel test execution.

ProChek reduces or even eliminates the need for expensive test equipment in fabrication process characterization. Testing is performed using multiple precision stress-and-measurement instruments embedded in a powerful yet compact unit which includes a graphical user interface setup and control application and results analysis tools. The ProChek platform and the host software are universal and can be used with different types of test chips across different processes and fabrication runs. The ProChek platform is extremely small (less than 14 cm x 17 cm x 4 cm, and weighs about 610 g) yet comprises instrumentation comparable to larger (and more expensive) rack-mounted equipment, making it a simple matter to move ProChek from a probe station in one lab or floor area to another, as needed.

You can choose to interface your wafer-based test structures directly to the ProChek platform or you can embed them within a customized test 'coupon' which includes on-chip switches, control logic, and heaters. The interface from ProChek to the probe station consists of a test interface card mounted on the ProChek platform and connecting to the prober via a set of high quality cables or through a direct-dock system.

ProChek wafer probe interface

ProChek wafer probe interface

Using a ProChek test coupon as the test chip on the wafer minimizes the signals required to be transmitted across the interface because a serial data stream is sent from the ProChek system to the test coupon, where decoding and selection logic is used to address specific devices-under-test (DUTs) on the test coupon. A standard test chip normally requires a separate interface signal for each terminal of each DUT, and the address decoding occurs on the test interface card on the ProChek platform. Whether you use your existing test structures or a ProChek test coupon, the tight integration across the instrumentation embedded in a single ProChek platform enables an intuitive software interface so that programming using either predefined or user-specified test scenarios is quick and straightforward. ProChek is equipped with accelerated stress test setups targeting reliability concerns such as negative and positive bias temperature instability (NBTI, PBTI), time-dependent dielectric breakdown (TDDB), hot carrier (HC) damage, electromigration (EM), and stress migration (SM). ProChek even supports 'fast NBTI/PBTI' measurements, observing the sub-microsecond onset of annealing effects, because it can switch from stress to measurement mode without missing a beat.

Accuracy and Performance to Meet the Market's Needs

ProChek is designed to deliver the essential process-level characterization data to both the fabless IC vendor and the foundry. Fabless manufacturers and ASIC designers know that their foundry cannot always supply them with all the device-level characterization data they need to maximize IC performance, yield, and reliability. Foundries and integrated device manufacturers (IDMs) need to measure and monitor each fabrication process to ensure that any drift or excessive variations are quickly understood and addressed. For companies and organizations where electronic reliability and lifetime performance is of paramount concern, characterization of IC manufacturing processes is a must.

With its accurate instrumentation, portable hardware, flexible interface, and easy-to-use software, ProChek fits – literally and figuratively – into virtually any process-level characterization flow

Optional ProChek Test Coupon for Further Test Optimization

With the innovative ProChek test coupon option, ProChek becomes even more cost-effective and time-efficient. Together the ProChek platform and test coupon comprise a comprehensive solution that delivers results for some of the most difficult device-level characterization tasks. The test coupon is manufactured using the target fabrication process and can contain multiple arrays of test structures to be characterized under various conditions. In addition to the test structures, the test coupon incorporates an on-chip switching matrix to access, control, and observe the behavior of these test structures as they are stressed in parallel and measured individually. Two test coupon configurations are available to meet different cost and performance targets:

  1. All the test coupon functionality is integrated on a single chip to maximize precision and test throughput; this approach minimizes the interfacing overhead since all the selection and switching mechanisms are on the test coupon itself, and also eliminates the need to use a heated wafer check if the ProChek heaters are used; and
  2. For characterization and qualification of newer processes, or for test chips without the embedded ProChek switching matrix, the device selection and addressing is performed on the test interface card mounted on the ProChek platform.

Regardless of the selected method, ProChek can dramatically lower the overall test cost and quickly deliver test results for statistical analysis.

Please click here to contact us directly for more information, or follow the links below.

Product briefs


  • Innovative Wafer-Level Reliability Methods using ProChek™
    • Click here to download Dr. McPherson’s webinar presentation (PDF)
    • Click here to download Dr. Manhaeve’s webinar presentation (PDF)
    • Click here to download the audio/video recording of the webinar (ASF)
  • Rapid Collection of Device-Level Reliability Data
    • Click here to download the webinar presentation (PDF)
    • Click here to download the audio/video recording of the webinar (WMV)
  • BEOL Reliability of Nanoelectronic Devices
    • Click here to download the webinar presentation (PDF)
    • Click here to download the audio/video recording of the webinar (WMV)
  • Semiconductor Fabrication Process Characterization Challenges 
    • Click here to download the webinar presentation (PDF)
    • Click here to download the audio/video recording of the webinar (WMV)
  • IC Characterization with ProChek, a Compact Benchtop System
    • Click here to download the webinar presentation (PDF)

White Papers and Application Notes

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